Advanced High-performance Bus (AHB), defined by the ARM AMBA specification and AHB Multilayer Interconnect, is an interconnection scheme that enables parallel access paths with efficient and smooth communication between various modules and components within the chip. SmartDV offers a complete, scalable, and silicon-proven solution for AHB Multilayer Interconnect. SmartDV’s AHB Multilayer Interconnect design IP core is highly customizable to optimize design area, power, and performance for both ASIC and FPGA flows, providing flexibility to adapt to specific design requirements.
Map User Interface signals with the AHB signals using a Control Logic
Configurable Data and Address Bus
Choose between Round-robin or Priority-Based Arbitration per Slave Selection
Full Protocol Support for Burst Transfers and Responses
Enhanced Throughput and Reduced Arbitration Overhead between Masters by conducting arbitration at each Slave port
AMBA 5 AHB Specification
AMBA 3 AHB specification
AMBA 2 AHB specification
All major EDA synthesis, simulation, and linting flows